The embedded systems industry is moving towards the integration of higher performance, yet less reliable electronic components into new product generations. Technology and voltage scaling increased dramatically the susceptibility of new devices not only to Single Bit Upsets (SBU), but also to Multiple Bit Upsets (MBU). However, the system reliability assessment at the design phase of fault-tolerant computer systems is a complex and critical task. In this context, it is mandatory to enhance reliability analysis and evaluation techniques at early-stage of the system development. In this paper, we present a technique for reliability evaluation of embedded systems at early-stage by taking into account the application behavior and SBU/MBU phenomena. Instead of using the random fault injection, our approach models the architecture behavior under real working conditions. Our results demonstrate the efficiency of the proposed fault injection simulation platform for early-stage reliability studies.