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Hardware resource estimation for heterogeneous FPGA-based SoCs


The increasing complexity of recent System-on-Chip (SoC) designs introduces new challenges for design space exploration tools. In addition to the time-to-market challenge, designers need to estimate rapidly and accurately both performance and area occupation of complex and diverse applications. High-Level Synthesis (HLS) has been emerged as an attractive solution for designers to address these challenges in order to explore a large number of SoC configurations. In this paper, we target hybrid CPU-FPGA based SoCs. We propose a high-level area estimation tool based on an analytic model without requiring register-transfer level (RTL) implementations. This technique allows to estimate the required FPGA resources at the source code level to map an application to a hybrid CPU-FPGA system. The proposed model also enables a fast design exploration with different trade-offs through HLS optimization pragmas. Experimental results show that the proposed area analytic model provides an accurate estimation with a negligible error (less than 5+) compared to RTL implementations.
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hal-03388517 , version 1 (20-10-2021)



Mariem Makni, Mouna Baklouti, Smail Niar, Mohamed Abidi. Hardware resource estimation for heterogeneous FPGA-based SoCs. ACM Symposium On Applied Computing 32nd, SAC'2017, Apr 2017, Marrakech, Morocco. pp.1481-1487, ⟨10.1145/3019612.3019683⟩. ⟨hal-03388517⟩
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