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A new memory reliability technique for multiple bit upsets mitigation

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Abstract

Technological advances make it possible to produce increasingly complex electronic components. Nevertheless, these advances are convoyed by an increasing sensitivity to operating conditions and an accelerated aging process. In safety critical applications, it is vital to provide solutions to avoid these limitations and to guarantee a high level of reliability. In most of the existing methods in the literature only Single Event Upsets (SEU) are assumed. The next generations of embedded systems must on one side support Multiple-Bit Upsets (MBU) and avoid to induce a significant memory and processing overheads on the other side. This paper proposes a new method to increase the reliability of SRAM, without dramatically increasing costs in memory space and processing time. Our method, named DPSR for Double Parity Single Redundancy, offers a high level of reliability and takes into fault patterns occurring in real conditions
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Dates and versions

hal-03522687 , version 1 (12-01-2022)

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Alexandre Chabot, Ihsen Alouani, Smail Niar, Reda Nouacer. A new memory reliability technique for multiple bit upsets mitigation. 16th ACM International Conference on Computing Frontiers, Apr 2019, Alghero, Italy. pp.145-152, ⟨10.1145/3310273.3321564⟩. ⟨hal-03522687⟩
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