AS8‐static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement - Université Polytechnique des Hauts-de-France Access content directly
Journal Articles IET Circuits, Devices & Systems Year : 2017

AS8‐static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement

Abstract

Soft errors in semiconductor memories occur due to charged particle strikes on sensitive nodes. Technology and voltage scaling increased dramatically the susceptibility of static random access memories (SRAMs) to soft errors. In this study, the authors present AS8-SRAM, a new asymmetric memory cell that enhances the soft error resilience of SRAMs by increasing the cells critical charge. They run Simulation Program with Integrated Circuit Emphasissimulations and system level experiments to validate the AS8-SRAM cell characteristics at circuit level and evaluate the energy and reliability effectiveness of an AS8-SRAM-based cache memory. The authors’ results show that AS8-SRAM presents up to 58 times less failures in time compared to six-transistor SRAM. Moreover, based on embedded benchmarks experimentations, AS8-SRAM achieves up to 22% reduction in energy-delay product without any considerable loss in performance.
No file

Dates and versions

hal-03402367 , version 1 (25-10-2021)

Identifiers

Cite

Ihsen Alouani, Mahmoud Elsharkasy Wael, Ahmed Eltawil, Fadi Kurdahi, Smail Niar. AS8‐static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement. IET Circuits, Devices & Systems, 2017, 11 (1), pp.89-94. ⟨10.1049/iet-cds.2015.0318⟩. ⟨hal-03402367⟩
9 View
0 Download

Altmetric

Share

Gmail Facebook X LinkedIn More